Field of the Invention
The present invention relates to semiconductor package technology, and in particular to a fan-out package structure.
Description of the Related Art
In recent years, as electronic products have been become increasingly multifunctional and have been scaled down in size, there is a desire for manufacturers of semiconductor devices to make more devices that are formed on a single semiconductor wafer, so that the electronic products that include these devices can be made more compact. In response to such demands, a Package-on-package (PoP) technique was developed. The PoP technique enables two or more packages to be installed atop one another, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in electronic products, such as mobile phones, personal digital assistants (PDAs), and digital cameras.
In such a PoP structure, through vias (which are sometimes referred to as through package vias (TPVs) or through interposer vias (TIVs)) which pass through a molding compound are typically employed to electrically connect the stacked packages. The formation process for TPVs/TIVs at least includes a lithography process to form TPV/TIV openings and a plating process to fill these openings with a conductive material. A molding process and a grinding process are then performed to form the TPVs/TIVs.
However, such processes for the formation of TPVs/TIVs are complicated and expensive. As a result, it is difficult to reduce manufacturing costs for semiconductor packages. Thus, a novel semiconductor package structure is desirable.